The present invention is directed to control circuits, and more particularly to an improved synchronous control circuit for providing accurate current control outputs.
The following U.S. Patents were considered during the preparation of the present disclosure: U.S. Pat. Nos. 3,294,981; 3,418,495; 3,657,569; 4,206,417; 4,425,613; 4,456,872; 4,829,259; 4,841,207; 4,885,522; and 4,902,944.
Various control circuits designed specifically for current mode control have recently been developed because of the various advantages of current mode control over conventional voltage mode control. A basic control circuit for current control is illustrated in FIG. 1. The circuit is shown as a half bridge circuit for illustrative purposes, it being understood that DC regulator and full bridge circuits are equally well known, as will be more fully evident hereinafter. As shown in FIG. 1, a pair of transistor switches A and B are alternately turned on and off so that the V.sup.+ and V.sup.- supply rails are alternately connected through the inductor L to a low pass filter C so as to generate the square wave Vin at the input of the inductor as shown in FIG. 2(a). Since there can be high dissipation losses of energy across the transistors when they are being switched between the open and closed states the switching should occur as quickly as possible to minimize this dissipation, with FIG. 2(a) showing the switching occurring with no dissipation and thus in an idealized form. As the transistors A and B alternately switch on and off by the switcher control, a square wave voltage V.sub.L is provided across the inductor, as indicated in FIG. 3, wherein V.sub.L, the voltage, across the inductor is simply V.sub.in minus the voltage output of the LC filter, V.sub.Z. V.sub.Z is substantially constant relative to the switching frequency although it is slowly varying at the low base-band frequencies passed by the low pass filter C. Thus, as described herein within each cycle of the switching frequency the signal is considered substantially constant so that it functions as an offset to the V.sub.in voltage. The current through the inductor, shown as i.sub.L in FIG. 4(a), will thus ramp up when V.sub.L is positive and ramp down when V.sub.L is negative, thereby producing the triangular waveform.
The switching circuit can be operated either at a fixed frequency, where the period of the triangular wave is fixed, or at a variable frequency, wherein the period of the triangular wave can vary. If during an on-off cycle the transistor A is on longer than the transistor B, the positive portion of the cycle will be greater than the negative portion, as indicated in FIG. 2(b). Conversely, during the on-off cycle transistor A is on for less time than transistor B, the positive portion of the cycle will be less than the negative portion. Consequently, the time the inductor current ramps up during a cycle will likewise vary, as illustrated in FIG. 4(b). The duty cycle (the amount of time the switch A is on during each period of the triangular wave) can be controlled to provide a duty cycle modulator.
In many instances, for example in a current supply for gradient coils of an MRI system, it is desirable that the triangular waveform be such that the resulting average base-band current of the waveform provided to the load Z.sub.L in FIG. 1 follows a given or prescribed slowly varying input signal (and yet remain substantially constant within cycle) so that the power delivered to the coils remains substantially fixed. However, the average current can vary with variations in the supply voltages (V+and V.sup.-), the load voltage V.sub.L across the inductor, variations in the maximum and minimum peak values of the triangular current provided through the inductor L, and variations in the frequency and duty cycle of the triangular waveform.
Various approaches fix one of these variables but are unsuccessful in fixing the other variables. For example, fixing the maximum and minimum peak values, i.e., the peak to peak ripple (PPR), for each cycle of the triangular wave output, as indicated by FIG. 5 would fix the average current value, but would require the length of the on and off portions of each period to vary (as illustrated by the two successive, but different periods T1 and T2 of FIG. 5) as the supply voltages V.sup.+ and V.sup.- vary since the positive slope m.sub.1 of the triangular wave (di/dt) is a function of (V.sup.+-V.sub.L )/L, while the negative slope m.sub.2 is a function of (V.sub.L -V.sup.-)/L. Thus, as the supply voltages vary, the positive and negative slopes of the triangular current waveform vary so that the frequency of the waveform varies. The same results occur where one of the peaks If instead of controlling the upper and lower peak current values, one or the other is fixed as a defined switching threshold, the switching frequency may also be synchronized to an external clock. However, in the latter case, the average output current will change if the load and power supply voltages change. Referring to FIG. 4(b), the latter shows a more general example of inductor current changes as a function of inductor voltage when the duty-cycle and period of the waveform changes. The waveforms shown in FIG. 4(b), the latter shows a more general example of inductor current changes as a function of inductor voltage when the duty-cycle and period of the waveform changes. The waveforms shown in FIG. 4(b) are not necessarily associated with any particular control scheme.
In addition other problems arise with current mode converters. For example, as described in Application Note "Modelling, Analysis and Compensation of the Current-Mode Converter" U-97 (pp. 9-87 through 9-92) and U-100A (pp. 113-115) published by Unitrode Integrated Circuits of Merrimack, NH (hereinafter the "Application Note"), at least in the case of synchronous, peak current sensing, current mode converters other disadvantages include (1) open loop instability above 50% duty cycle, (2) less than ideal loop response caused by peak instead of average inductor current sensing, (3) tendency towards subharmonic oscillation, and (4) noise sensitivity, particularly when inductor ripple current is small.
Accordingly, one approach to solve at least some of the above-noted problems is described in the Application Note. Specifically, a compensating signal is provided having an amplitude over the period of the clocking cycle which decreases at a linear rate (slope "m") at one-half the desired slope "m.sub.2 " of the negative going portion of the steady state waveform as best seen in FIG. 6. The DC voltage regulator circuit described in the Application Note is reproduced in FIG. 7. The compensating signal is provided by the single resistor Rs at the non-inverting input of the comparator shown at COMP. The compensating signal is used to define the peak current at which the transistor A is switched from on to off so that as the duty cycle increases the peak current at which the transistor switches decreases. In this way the peak switching current is a function of the duty cycle. The article suggests that providing the compensating signal provides a constant average current regardless of the duty cycle as shown in FIG. 6. Further, the linear ramp of the compensating signal insures convergence of the current waveform even when the duty cycle is over 50% although the convergence takes place over several cycles with the circuit approaching instability (subharmonic oscillations) at a duty cycle of 1. Thus, some undesirable ringing takes place.
The Application Note suggests that in order to insure current loop stability and improve dynamic performance, the slope m of the compensation ramp can be increased greater than one-half of the negative slope m.sub.2 of the steady state current waveform to minimize ringing, with the best possible transient response occurring when the slope m of the compensation signal is set to be equal to the negative slope m.sub.2 of the inductor current ramp, which is analogous to critically damping the inductor current, allowing the current to correct itself in exactly one cycle. But the article states that while this minimizes inductor current ringing, it has little bearing on the transient response of the voltage control loop itself since it will not provide the constant average current achieved by the m=m.sub.2 /2 solution.
Several observations can be made about the above approach. First, the choice of the slope of the compensating signal is a tradeoff between good average current tracking (requiring a setting of the slope m=m.sub.2 /2), and good dynamic performance of the circuit (requiring a setting of the slope m=m.sub.2). Secondly, as a DC regulator the slope m.sub.2 is treated as fixed since it is solely dependent on input and load voltages. Specifically, as shown the slope m.sub.2 is shown as always being the same, irrespective of the slope m.sub.1 so that the average current can be maintained constant irrespective of the slope m.sub.1. It is not apparent from the description of the compensation circuit in the Application Note that the slope of the compensation signal will adapt to changes in m.sub.2 which can be brought about with fluctuations in the input and load voltages in the case of the DC regulator and additionally, the negative voltage rail V.sup.- in the case of the half or full bridge. Finally, while the comparisons are made between the m=m.sub.2 and m=m.sub.2 /2 solutions, it is not clear that using the resistor R.sub.s will provide the desired steady state solution, not only in terms of the slope m.sub.2, but also the amplitude level of the sloped portion of the signal.